Jiang, Fish
7490357f22
vulkan: skip unneeded MoE work in mul_mm coopmat1 path ( #25483 )
2026-09-17 09:53:07 +03:00
Jiang, Fish
1945e09203
vulkan: add f16 B-type matmul pipelines and warp tile size tuning for Intel coopmat1 ( #27471 )
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* vulkan: add f16 B-type matmul pipelines and warp tile size tuning for Intel coopmat1
* simplify mmp selection in mul_mat_id per review comment
* vulkan: enable f16 B-type pipeline for dense matmul on all vendors (MoE stays Intel-only)
* vulkan: add missing ocp_fp4 branches, restrict required_subgroup_size to Intel, fix mmp selection
* refine mmp selection in mul_mat_id
* add f16B pipeline selection just like q8_1
* update f16B pipeline selection in dense function
2026-09-09 09:03:32 +03:00
Jiang, Fish
9b0a2ce859
vulkan: add SHMEM_STRIDE_PAD/APPLY_SLM_A_RESHAPE for coopmat1 on Intel Xe ( #25380 )
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* vulkan: add SHMEM_STRIDE_PAD/APPLY_SLM_A_RESHAPE for coopmat mul_mm on Intel Xe
* vulkan: fix shmem estimate for Intel SHMEM_STRIDE_PAD=0 in matmul_shmem_support
* cacheline aligned for shared kvalues_mxfp4
* vulkan: fix OOB read in kvalues_mxfp4 init after cacheline padding
* vulkan: restrict SLM-A reshape to Intel Windows driver, revert mxfp4 cacheline padding
2026-08-15 11:35:05 +02:00
5a6a0dd7e1
vulkan: add INTEL_XE1 arch enum and enable coopmat1 on Intel Xe-LPG Plus ( #24404 )
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* vulkan: add INTEL_PRE_XE2 arch enum and enable coopmat1 on Intel Xe-LPG Plus (1/3, Xe1-ARLH)
Co-authored-by: Xia, Jie <jie.xia@intel.com >
Co-authored-by: Liu, Russell <russell.liu@intel.com >
* Address comments of bf16 and trailing whitespace
* Rename INTEL_PRE_XE2 to INTEL_XE1 and remove driver workaround
* Add Windows driver check
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Co-authored-by: Xia, Jie <jie.xia@intel.com >
Co-authored-by: Liu, Russell <russell.liu@intel.com >
2026-06-26 13:26:22 +02:00
Jiang, Fish