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Thiago PadilhaandGeorgi Gerganov
f91123d2d0
Build QSA blocks per sequence in token order and select complete blocks before expanding them to cache cells. Keep only the incomplete tail unconditionally visible and rotate pooled keys with the first token's full M-RoPE position. This prevents unified-cache sequences from sharing pooled indexer keys and avoids replacing padded tail entries with extra history tokens. Synthetic Qwen4 architecture, exact mask, F16 and Q8_0 state, sequence-copy, Metal, and AddressSanitizer checks pass. Assisted-by: Codex qwen4exp: support independent PLE embedding widths Size the PLE key and value projections from the concatenated n-gram embedding instead of assuming it matches the model hidden width. Validate the head count before narrowing it to the stored type. Add a synthetic PLE model with a 64-wide embedding and a 256-wide hidden state, then verify inference and model roundtrip. Assisted-by: Codex qwen4exp: validate model metadata Reject invalid GDN, hyper-connection, QSA, and PLE dimensions during model loading instead of aborting later while building the graph. Validate PLE array lengths before copying them into fixed storage. The released configuration and synthetic Qwen4 architecture tests pass. Assisted-by: Codex qwen4exp: update indexer cache after sequence copies Treat cached indexer keys as unrotated data and apply pending cache updates alongside the attention and recurrent state. This copies indexer data during non-unified cross-stream sequence copies without applying RoPE shifts to raw keys. Assisted-by: Codex qwen4exp: enable recurrent state rollback Assisted-by: Codex qwen4exp: disable tensor split Assisted-by: Codex metal: align dynamic threadgroup memory Assisted-by: Codex metal: widen expert matmul thread index Assisted-by: Codex